Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a circuit for training/controlling a slew rate of data outputted from a semiconductor memory device.
A semiconductor memory device includes hundreds of memory cells, and the basic functions of the memory cells are to input/output data to write data in a memory cell or read data that has been already written in a memory cell. Semiconductor memory devices including Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate (DDR) DRAM, and DDR3 DRAM may perform a variety of different functions, but their basic characteristics such as having memory cells and refreshing the memory cells are similar.
Semiconductor memory devices may be developed for writing/reading data at a high speed and reducing production costs while retaining the inherent characteristics.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device. The conventional semiconductor memory device includes a command and address buffer 102, a row decoder 103, a column decoder 104, a DRAM core 105, a data input buffer 107, a data input register 108, a data output register 109, a data output buffer 110. Since the functions of the above-mentioned constituent elements are obvious to those skilled in the art to which the present invention pertains, further description of them will not be provided herein and only a constituent block related to an exemplary embodiment of the present invention will be described briefly hereafter.
The DRAM core 105 includes a DRAM memory cell and a sense amplifier which amplifies a data stored in the memory cell. The row decoder 103 and the column decoder 104 perform a function of selecting the memory cell on a position corresponding to an address and a command transferred from the outside. Here, the command includes commands in charge of row access and column access in the operation of a DRAM device, such as a Row Address Strobe (RAS) signal, a Column Address Strobe (CAS) signal, and a Write Enable (WE) signal.
As a row address is inputted at the moment when the row address strobe (RAS) signal is enabled, and the row decoder 103 decodes the received row address to enable a plurality of memory cells. Data stored in the DRAM cells are amplified by a sense amplification operation of the DRAM core 105. In short, a sense amplifier inside the DRAM core 105 performs a function of a data cache which waits for a read operation or a write operation while retaining amplified data.
In case of a read operation, when a column address strobe (CAS) signal is enabled, a column address is decoded simultaneously and data are outputted from a sense amplifier group which performs a function of a data cache to an internal data bus. The outputted data are stored in the data output register 109. The data stored in the data output register 109 are outputted through the data output buffer 110 at a predetermined time.
FIG. 2 is a circuit diagram illustrating a circuit of the conventional data output buffer 110 illustrated in FIG. 2.
The data output buffer 110 includes a pre-driver 201 and a main driver 202. The pre-driver 201 determines the logic state of an outputted data, and when no data is outputted it keeps the main driver 202 at a high impedance state which is a Hi-Z state. Here, a driving power source VDDQ is a high-voltage power source, and a ground power source VSSQ is a low-voltage power source.
When an L (logic low) state value is inputted to an up data input part UP_DATA of the pre-driver 201 and a H (logic high) state value is inputted to a down data input part DN_DATA of the pre-driver 201, the H state value is inputted to a PMOS gate of the main driver 202 and the L state value is inputted to an NMOS gate of the main driver 202. Therefore, an output end OUT of the data output buffer 110 maintains a high impedance state (a Hi-Z state) which is neither an H state nor an L state.
Meanwhile, when an H state value is inputted to the up data input part UP_DATA and the down data input part DN_DATA of the pre-driver 201, an L state value is inputted to the PMOS and NMOS gates of the main driver 202. Therefore, an H-state data may be outputted from the output end OUT of the data output buffer 110. Conversely, when an L state value is inputted to the up data input part UP_DATA and the down data input part DN_DATA of the pre-driver 201, an H state value is inputted to the PMOS and NMOS gates of the main driver 202. Therefore, an L-state data may be outputted from the output end OUT of the data output buffer 110.
A data DATA outputted from the data output buffer 110 may be outputted to an input/output pin 106. Here, the slope of an outputted signal changing between L and H states is referred to as a slew rate. The slew rate is represented, for example, by 3V/ns, which means that a signal rises/falls by 3V in 1 nanosecond (ns).
The slew rate is determined by the size of a transistor in the pre-driver 201 illustrated in FIG. 2. The slew rate may be determined based on the size of the transistor, and also based on diverse norms such as resistance. In this embodiment, however, it is assumed that the slew rate is determined based on the size of the transistor.
According to the conventional technology, the slew rate is provided as a fixed value which is determined at the stage of designing a DRAM device. Therefore, when the slew rate is high, signal quality is deteriorated due to bounce noise, and when the slew rate is too low, signal quality is deteriorated because the variation width of access time becomes too wide. Here, the signal quality may be signal integrity. When signals are outputted for a predetermined time period, a time occupied by outputted data and a time occupied between the outputted data are determined in the time period. Here, fine signal integrity signifies that the time occupied by the data is relatively longer than the other.
However, since the slew rate is provided as a fixed value determined when the DRAM device is designed according to the conventional technology, the slew rate cannot be controlled after the DRAM device product is designed, which may be a drawback of the conventional technology.